this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number for guaranteed specification limits. 1 www.visha y .com vishay siliconix spice device model SI4459ADY document number: 68446 s-81895 ? p-channel 30-v (d-s) mosfet characteristics ? p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model descri bes the typical electrical characteristics of the p-channel vertical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the pulsed 0-v to 10-v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capac itance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c gd model. all model parameter values are optimized to provide a best fit to the me asured electrical data and are not intended as an exact physical in terpretation of the device. subcircuit model schematic
2 vishay siliconix spice device model SI4459ADY www.visha y .com document number: 68446 s-81895 ? specifications (t j = 25 c unless otherwise noted) parameter symbol test condition simulated data measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = ? 250 a 1.7 v v gs = ? 10 v, i d = ? 15 a 0.0038 0.0039 drain-source on-state resistance a r ds(on) v gs = ? 4.5 v, i d = ? 10 a 0.0062 0.0062 forward transconductance a g fs v ds = ? 10 v, i d = ? 15 a 37 24 s diode forward voltage v sd i s = ? 3 a ? 0.70 ? 0.71 v dynamic b input capacitance c iss 6043 6000 output capacitance c oss 893 860 reverse transfer capacitance c rss v ds = ? 15 v, v gs = 0 v, f = 1 mhz 768 790 pf v ds = ? 15 v, v gs = ? 10 v, i d = ? 20 a 116 129 total gate charge q g 62 61 gate-source charge q gs 16.5 16.5 gate-drain charge q gd v ds = ? 15 v, v gs = ? 4.5 v, i d = ? 20 a 23.5 23.5 nc notes a. pulse test; pulse width 300 s, duty cycle 2%. b. guaranteed by design, not s ubject to production testing.
3 vishay siliconix spice device model SI4459ADY www.visha y .com document number: 68446 s-81895 ? c unless otherwise noted)
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